Natural phenomena such as electric and magnetic fields, fluid flows, sound waves, and heat flow are, at any given moment in time, represented as spatially distributed data in a three dimensional manner by a number or set of numbers whose indices represent spatial positioning along three mutually orthogonal axes. On occasion, a fourth dimension, namely time, must also be considered. To date, scientists and other computer users wishing to solve partial differential equations that involve spatially distributed data such as Poisson's or Maxwell's equations have had limited data processing capabilities because prior art Processor systems and processor arrays have been limited to two-dimensional architectures.
Prior art attempts at solving three-dimensional equations utilizing purely one or two-dimensional arrays have yielded processing systems requiring a large amount of "processor overhead" to calculate an index or address pointer to the second or third dimension of the spatial data which must be stored in memory and not in a processor. For example, in a traditional single processor computer, computing the X and Z dimension indices requires up to three multiplications and two addition steps. On a two-dimensional computer, although the X and Y axes are directly accessible, the Z pointer must be calculated which still requires up to one multiplication and one addition.
Prior art attempts at dealing with three-dimensional data also include the utilization of an interconnection arrangement such as that disclosed in U.S. Pat. No. 4,814,973 in which routers may be instructed to switch data between processor cells in a fashion that mimics the behavior of a three-dimensional processor array. Routers, however, require a large amount of processor overhead to move data between the various processor cells. In addition, supporting control circuitry is required to perform the switching function. System throughput or bandwith is significantly compromised by the router overhead, and system cost and reliability are compromised due to the necessity of including the routers and associated control circuitry.
Additionally, many parallel processing problems require more problem nodes than the number of available processor cells in the processor array. In such situations, it is desirable to avoid requiring the application programmer to adjust the problem space to fit a given processor array. Rather, the application programmer should be insulated from restrictions in the size of the processor array and should have to specify only the size of the problem space. Further, it is necessary to be able processing programs on any size processor array to maintain compatibility between various processor systems having varied processor array sizes.